I2C

Top  Previous  Next

Extracts all I2C events including START,STOP,ACK,NAK. Also sends separate events for special codes, address, R/W and data fields. Note that framing is inherent in this protocol so the preparser sends START and STOP events to your plug-in.

 

Configuration Options provided by the pre-processor

Clock(SCL)
Selects which physical channel to assign to the CLOCK
 
Data(SDA)
Selects which physical channel to assign to the DATA
 
Glitch Filter
Selects the amount of noise filtering.   Should be set to 50ns for low
speed operation and reduced for faster speeds
 
Skip Bits (to sync partial frame)
Specifies how many bits to ignore at the start of the buffer.
Useful for syncing up when capture starts mid-frame
 
Decode Addr 000-0001-d as
Selects between the standard I2C decoding for this address range or decoding it as
normal 7 bit devices.
 
Decode Addr 000-001X-d as
Selects between the standard I2C decoding for this address range or decoding it as
normal 7 bit devices.
 
Decode Addr 111-11XX-d as
Selects between the standard I2C decoding for this address range or decoding it as
normal 7 bit devices.
 
Decode HS Master Codes as
Selects between the standard I2C decoding for this address range or decoding it as
normal 7 bit devices.
 
Decode 10bit Codes as
Selects between the standard I2C decoding for this address range or decoding it as
normal 7 bit devices.
 
Truncated fields
Specified whether to show truncated/partial fields or not.  1 bit truncated fields
common and unavoidable so the options include showing only if > 1 bit.

Events

The built-in I2C preparser generates 16 events.  A single event is sent at a time.  The event code is placed in byte[6] and is encoded as shown below:

START  (0)

Generated whenever the start condition is detected on the bus.

START-BYTE  (1)

Generated when the first byte holds the special code: 0000 0001.  Under normal operation, the plug-in should expect to receive a NAK event followed by a Repeated start (Sr) event and then any normal ADDRESS event.

ADDRESS  (2)

Generated for all general 7 bit addresses in the first byte. byte[0] contains the entire 8 bit value of the first field.  This includes the 7 bit address in the upper 7 bits and the direction bit in the LSB.  One would normally ignore the direction bit and just grab the address at this point.  A DIR event will follow shortly to timestamp the direction bit.  It will include the same data[0] as this call, allowing you to handle the address and/or direction in either/both calls.

GENERAL-CALL  (3)

Generated when the GENERAL-CALL code ( 0000 0000) is detected in the first byte.  Under normal operation, the plug-in would then expect to receive an ACK event followed by the general-call sub code in a DATA event.

CBUS  (4)

Generated when the first byte contains the CBUS code (0000 001X).  Following this event, the preparser ignores all bus activity until a STOP condition is detected. The plug-in will receive a STOP event when the CBUS activity completes.

HSMASTER  (5)

Generated when the special HSMASTER code (0000 1XXX) is detected in the first byte.  The XXX is the master's code.  Data[0] contains the full 8 bit code. Under normal operation the plug-in would expect this to be followed by a NAK event, a repeated start event and then a normal 7bit address event.  High speed operations remains in effect until a STOP event is received.

RESERVED  (6)

Generated when an address within the 2 reserved ranges is detected in the first byte.  data[0] contains the address and direction bit. A DIR event will follow with direction bit's timestamp and the same data.

10BITADDR  (7)

Generated when the special 10Bit Code (1111 0XX) is detected in the upper 7 bits of the first byte.  Notice the XX bits are the upper 2 bits of a 10 bit address. The remaining 8 bits come from the next byte or are assumed from the context. The pre-parser does not look at the direction bit, the next byte and/or the presence of a Repeated start to decode the actual 10 bit address.  It simply reports the detection of this code.  Of course, additional events will follow to report DIR, data and start/repeated starts so that a plug-in could determine the full 10 bit address just as a slave device would. 

DIR  (8)

Generated for the Direction bit.  The LSB of data[0] indicates the bit value; 1=> Read, 0=> Write.  The upper 7 bits of data[0] contain the 7bit address this DIR event refers to.  It can be ignored as it was sent to the ADDRESS event earlier.

ACK/NAK  (9)

Generated for the Ack/Nak bit.  The LSB of data[0] indicates the bit value; 1=> NAK, 0=> ACK

DATA  (10)

Generated at the start of each byte of data in the payload. data[0] contains the data.

STOP  (11)

Generated whenever the stop condition is detected on the bus.

Truncated  (12)

Generated when a partial byte of data was received.

RESTART (13)

Generated whenever the start condition is detected on the bus WITHOUT a preceding STOP condition. This is called a Repeated Start.

FIELD-IDLE (14)

Generated to timestamp the end of a byte of data.  Usually used to allow display of idle periods between the last data bit and the ACK.NAK bit.